Optimizing ECG signal analysis by building FPGA-based accelerators using High Level Synthesis - Κολιογεώργη, Κωνσταντίνα (Εθνικό Μετσόβιο Πολυτεχνείο. Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών. Τομέας Τεχνολογίας Πληροφορικής και Υπολογιστών, 2016)
One of the most fundamental and crucial biological signals for monitoring and assessing the health condition of a person is the Electrocardiogram (ECG) due to its inherent relation to heart physiology. Consequently, its analysis and interpretation has been established as an important field in modern medicine and this in turn has spawned various inter-disciplinary studies including digital processing analysis of the signal. Given the complexity of deriving exact models for assessing and predicting the heart's condition, machine learning techniques have recently dominated the field of ECG analysis. Support Vector Machines based classifiers especially, have grown very popular as the key element of machine learning based ECG analysis due to their capability of accurate prediction and their interesting computational structure. Last but not least, constant monitoring and real-time heart condition assessment have imposed new requirements for acceleration and low power execution of a digital ECG analysis ow system. Taking all these into consideration, in this work we focus on utilizing High Level Synthesis capabilities to produce efficient SVM hardware accelerators. Our case study is arrhythmia detection using MIT-BIH ECG signal medical database. We show that as a first step, the original code under acceleration can be re-structured in order to create instances which are efficiently transformed into a HW accelerator. As a second step, an exploration is performed on the transformed code in order to determine which HLS directives produce the best outcome in terms of various performance and resources utilization metrics. Our combined analysis shows that we can achieve results of up to 99% execution latency gain compared to the original SVM code and the designer is given a set of Pareto Optimal design points in order to decide the best trade-off between gains in latency and increase in utilized FPGA HW resources.